An analog-to-digital converter (ADC) for high frequency analog signals is invariably implemented using a ‘flash’ architecture where the applied analog input signal is compared against an array of equally spaced static voltage references. A separate voltage comparator is used to compare the analog input signal against each voltage reference. The output from the comparator is normally a logical signal, of value ‘1’ or ‘0’, indicating whether the analog input signal is higher or lower than the reference voltage. The comparator outputs are then decoded to produce a digital code word which is a representation of the analog input signal. Normally the comparator outputs are only sampled at particular time instances, using a suitable repetitive clock signal, so that a well defined time correlation can be achieved between the analog input signal and the digital output code.
In a conventional flash ADC every time the conversion accuracy is increased by 1-bit the size of the number of static voltage references and the number of comparators to perform the analog to digital operation must all increase by a factor of two. The complexity of the decoder to produce the output digital word from the ADC also increases by a factor of two. In addition, the power consumption of the analog interface circuit to the ADC increases since it has to drive more comparators whilst still maintaining adequate linearity specifications.
The result is an increase in both the area of the ADC by up to a factor of two for every 1-bit increase in the ADC accuracy together with a significant increase in power consumption in the analog interface circuits and the comparator array.
A technique for extending the accuracy of an ADC without significantly increasing complexity and without placing additional requirements on the analog interface is therefore extremely desirable.